During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results:

Verification Methodology - 41%

SystemVerilog Tutorials - 31%

e Tutorials - 13%

Interviews - 12%

Lightweight Articles - 4%

Yes we've upgraded our website! We hope you like the new look and feel. A new decade has just begun and we feel that 2010 is going to be a great year. So what can we expect in 2010? Yet again, the EDA industry has termed a new acronym for us - UVM. VMM and OVM are so 2009... UVM (Unified Verification Methodology) is the new name of the game. Well, at least as far as SystemVerilog users are concerned. Take some OVM, add a bit of VMM, one month in the oven, put some sugar on top and you got yourself a "brand new" industry standard methodology for System Verilog. We talked about this last year - how convergence on methodology is inevitable - and we're glad to see it starting to happen more quickly than we had thought.