Introducing Philip Americus - a new guest blogger here on Think Verification. Phil is an ASIC veteran who's worked with every phase of ASIC design - from initial concept to tapeout, with an emphasis on verification, including management of both HW and SW engineers. This is his debut post on our website:
When I first started my Engineering career we had Verilog-95 and VHDL. Combine this with some wrappers, in C, Perl, or Csh, and we accomplished Verification just fine. As designs became larger and more complex, we continually felt a need to go to higher level programming models. In came Specman, SystemVerilog (Superlog!), SystemC, model checking, etc. to meet the challenge. Some companies embraced these new technologies and some stuck with the old.
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Great verification engineers know the secret - if they want to be successful they must also understand the essence of the entire chip design flow, from concept to working samples. Here are some great videos that will help you see the big picture a bit better.
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Have you ever watched Inside the Actors Studio? You know, the show where James Lipton hosts famous actors in front of a small audience of students? Remember?
Anyway, this is actually one of my favorite shows on TV (and there aren’t that many really). Towards the end of each show Lipton usually does the Bernard Pivot questionnaire “ he asks the celebrity a series of short questions such as what is your favorite word / curse word / sound and it’s really interesting and funny to hear the answers. I even learned that Natalie Portman and I have one thing in common “ our favorite curse word...
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As the EDA industry seems to be making moves towards a Unified Verification Methodology (OVM + VMM) we thought this would be a great opportunity to share a couple of things that have been on our wish-list for quite a while.
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3 years ago that was on our wish list. Now it is a reality - A modern programming environment for verifiers!
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