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Constraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really imply a very directed scenario. In most cases what we want to is to have a set of default constraints that give us a nice distribution of scenarios and values. We will then need to override the default set in some of our test cases by applying additional constraints, or reshaping the distribution or even removing previous constraints. SystemVerilog does not support advanced manipulation of constraints as much as e does (for example look up soft constraints and reset_soft() in e) but combined with some simple tricks that we''re going to show you here, you can get most of the things done quite easily:
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If you're familiar with SystemVerilog and taking your first steps in e (or vice versa) you might find this useful. Here are some of the most common method manipulations that you''ll need to master and how you should go about implementing them in e and SV:
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How to activate Specman Profiler? How to get rid of automatic vr_ad coverage? Let's find out.
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This example shows how to pack a struct into a list of Double Words (32 bit) keeping the original order. This time we got less talking, and more code:
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Before type-casting an e variable ("as_a"), we often want to check the validity of the operation (this is quite similar in concept to $cast in SystenVerilog). The reason is simple, in case the casting operation failed we would end up with a fatal error at run-time that otherwise could have been avoided. But how?
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Tutorials
