Think Verification - Tips & Insights on ASIC Verification

The Tipping Point

admin@thinkverification.com (Administrator) — Fri, 27 Aug 2010 12:03:31 +0000

A friend of mine once recommended me a book. It was The Tipping Point by Malcolm Gladwell. It sounded interesting, so I decided to put it on my reading list. Somehow the existence of my reading list came to the knowledge of a family member, I swear I don't know how. One thing led to another and by weird coincidence, on my next birthday I got this book as a present. I haven't yet found the time to read it from cover to cover, though I think I've read the first chapter a few times. I guess I'll just have to take it with on my next vacation.

Educate Yourself - SystemVerilog 101

admin@thinkverification.com (Administrator) — Sun, 03 Jan 2010 14:22:56 +0000

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language seems to be ubiquitous and all 3 big EDA vendors keep pushing it forward. Whether this is good or bad is an interesting question, but one thing is certain - if you consider yourself a modern verifier, you'd better get familiar with SystemVerilog unless you want to stay in the dark.

About UVM And You

admin@thinkverification.com (Administrator) — Mon, 01 Mar 2010 16:52:01 +0000

There’s been a lot of buzz about the UVM lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers questioned the need for adopting any verification methodology… Today, however, the question is entirely different – it is WHICH methodology to adopt. So as the UVM is gradually taking form and drawing the attention of verification stakeholders I think it’s a great time to stop and remind ourselves why we need a verification methodology in the first place, and more importantly - what makes a verification methodology so good that the only question about it would be “how quickly can I learn it”? I have identified 3 elements of a good verification methodology that work together, each on a separate track, to make it do its magic. The first element is Guidance, the second is Efficiency, and the third one – perhaps the most exciting one – is what I call The Real Added Value.

Let The New Game Begin

admin@thinkverification.com (Administrator) — Mon, 07 Jun 2010 14:02:12 +0000

Things are changing. The EDA industry is undergoing a paradigm shift. John Bruggerman’s visionary document talks about the application-driven market and how EDA should become its enabler and Janick Bergeron's inspiring talk at SNUG San Jose gives us a glimpse of the future of verification. One of the major challenges we’re already facing today is an increasing number of IP blocks in a single system. Designs are getting bigger and bigger, and the focus is shifting towards system level integration rather than “design creation”.

Is ABV Becoming Mainstream?

admin@thinkverification.com (Administrator) — Sun, 25 Apr 2010 13:06:02 +0000

Is Assertion-Based Verification (ABV) becoming mainstream? This question popped up today at Mentor’s ABV seminar. Assertions in general and ABV in particular make another approach that you can use to verify your design. Usually ABV alone is not sufficient, and is used alongside other verification approaches such as Coverage-Driven Verification, Directed Testing, Formal Verification, and Code Coverage. What’s good about ABV though, is that it’s the fastest tool around in terms of failure-to-root-cause time (also in your testbench!)

EndMaker: Make Your SystemVerilog Code Look Professional (Free Utility)

admin@thinkverification.com (Administrator) — Thu, 15 Apr 2010 12:46:25 +0000

This is a cool little utility that will make your SystemVerilog look much more professional. It simply adds an end-of-method identifier (label) to every task or function so that every endfunction turns into endfunction : function_name (with the appropriate function_name of course.. Duh!) and endtask turns into endtask : task_name. This really makes your code more readable and consistent.

AutoDup: Create Test Variants Quickly (Free Utility)

admin@thinkverification.com (Administrator) — Thu, 01 Apr 2010 15:12:50 +0000

Coverage driven verification has a big advantage – you can write a single test, and let run it several times with random seeds. Each run will generate a slightly different scenario – depending on the nature of the constraints you provided. I’ve talked about the pros and cons of excessive use of coverage driven methods here and here. Anyway, sometimes you just want to take an existing test and quickly create a number of variants off of it to make a small regression suite (that you might even throw away later on). For example – you could have a basic test that does some CPU writes and then drives random frames. During configuration you write to a register that sets the FIFO level and you want to have 10 different tests, each writes a different value to this register.

What Makes A Great Verification Team GREAT?

admin@thinkverification.com (Administrator) — Thu, 24 Dec 2009 17:10:32 +0000

Your tool provider won’t tell you that, nor will those fancy methodology books, but verification is not all about mastering technical skills. True, those will help you very much in your daily work but verification is first and foremost TEAM WORK. But not only that, there are several key factors, or qualities if you will, that really distinguish the great verification teams from the good ones. Here there are: