More articles : » Debug Like The Pro'sYou’ve developed a verification environment, hooked up the DUT, written a bunch of tests and alas! Simulations start to fail So just before you dive in, Think Verification’s tips department recommends the following: » Specman GUI TrickIf you’re using Specman GUI to run simulations you must have encountered this rather annoying feature before - When running several simulations during the same session, specman doesn’t clear the log file by default so what you get in the end is... » Get HookedChanging an existing eVC for new project requirements is a grueling task. It’s really painful for any eVC developer to witness his creation being torn apart by an end user, but a little prudence from the developer can result into longevity of eVC.... » Read/Write Registers From EverywhereHere’s something for the less experienced verifiers out there. I’ve been asked to help with this issue several times in the past so I guess some of you will find it useful. » Smart Constraints In SystemVerilogConstraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really... Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
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