Home Articles News We Hear Ya!


We Hear Ya! PDF Print E-mail
User Rating: / 3
Thursday, 08 April 2010 11:36


During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results:


Verification Methodology - 41%

SystemVerilog Tutorials - 31%

e Tutorials - 13%

Interviews - 12%

Lightweight Articles - 4%

Looks like most of you would like to learn more about advanced verification methodology, especially with SystemVerilog. That's a very clear message. We'll try to focus on that area in the coming months, and in the meantime we'd appreciate it if you could send us more specific requests (as some of you already have). You can also leave them as comments if you like.

In the meantime, if you haven't already seen our VMM Hackers Guide series, you might find it interesting.

And on that note - did you like our autodup utility? if you did, please drop us a line or leave a comment to encourage us to develop more stuff for you!


Oh, and have we ever mentioned how important t your feedback is to us? Wink

Seriously, even if you're not into the whole commenting thing please just devote 5 seconds of your time to take the poll (at the upper right of this page) to tell us what you think.


Happy Verifying!



More articles :

» What Makes A Great Verification Team GREAT?

Your tool provider won’t tell you that, nor will those fancy methodology books, but verification is not all about mastering technical skills. True, those will help you very much in your daily work but verification is first and foremost TEAM WORK....

» Smart Constraints In SystemVerilog

Constraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really...

» Plug, Play and Reuse!

Time to talk about module-to-system reuse, a very important topic. If you plan your verification environment properly (using one of the common methodologies in the market today or your own) you’ll be able to easily build a system level...

» About UVM And You

There’s been a lot of buzz about the lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers...

» To Randomize Or Not To Randomize

One of my former colleagues once revealed the fact that she had no less than 70 pairs of shoes. That’s right, seventy! She had been very good at her job and by no means had any plans to start her own shoe business so I asked myself why on earth...

Add comment

Security code

Copyright © 2018 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.