Home Tips EndMaker: Make Your SystemVerilog Code Look Professional (Free Utility)

Search

EndMaker: Make Your SystemVerilog Code Look Professional (Free Utility) PDF Print E-mail
User Rating: / 22
PoorBest 
Thursday, 15 April 2010 12:46

This is a cool little utility that will make your SystemVerilog look much more professional. It simply adds an end-of-method identifier (label) to every task or function so that every endfunction turns into endfunction : function_name (with the appropriate function_name of course.. Duh!) and endtask turns into endtask : task_name.  This really makes your code more readable and consistent.

How to use? very easy – download the file below and then simply run it on every file you wish to process, like this:

%./endmaker file.sv

 

Try it out now! Let us know what you think.

 

Note: when you save the file, sometimes an automatic file extension will be added, e.g. endmaker.txt. You can safely rename the file to get rid of it.


Attachments:
FileDescriptionFile size
Download this file (endmaker.txt)EndMakerAutomatic endfunction/entask label generator1 Kb
 
More articles :

» About UVM And You

There’s been a lot of buzz about the lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers...

» AutoDup: Create Test Variants Quickly (Free Utility)

Coverage driven verification has a big advantage – you can write a single test, and let run it several times with random seeds. Each run will generate a slightly different scenario – depending on the nature of the constraints you provided....

» Top 10 Verification Myths

Let’s unveil the truth behind some of the common myths out there!

» Another Step Forward For VMM

While the move from 1.0 to 1.1 and its later flavors did not involve a major paradigm shift, VMM1.2 (beta) introduces several fundamentally new concepts that you should be aware of. Some of the new concepts are the natural result of an evolving...

» We Hear Ya!

 During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results: Verification Methodology - 41%SystemVerilog Tutorials - 31%e Tutorials - 13%Interviews - 12%...

Add comment


Security code
Refresh

Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.