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Thursday, 20 May 2010 08:57


 
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» The Easy Way To Start Using OVM-e Sequences

Industry-standard methodologies are great, really. It would be so nice if our entire verification environment (VE) were OVM-e (eRM) compliant, wouldn’t it? But what if there are legacy components in our env that don’t follow any specific...

» My Story With Certitude

Long time no see. My website has been down for a while (technical issues - web experts contact me if you want to help) but now it's up again. And going through some of my old articles here (well, they're all old, I should probably do something about...

» Eternal Sunshine of the Verifier's Mind

To be successful in verification you not only need to possess the right technical skills, but you also need to possess the right mindset. Possessing the right mindset will lead you to success rapidly. Here are 3 things that I’ve found very...

» Educate Yourself - SystemVerilog 101

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get...

» Don't Be SYSsy

Anyone who’s ever worked with me knows that I have several weaknesses. One of them is extra sensitivity to things that reside under sys (global.sys) in Specman/e. If this is Chinese to you then you’re probably a SystemVerilog guy: "sys" is the...

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