More articles : » Cool Things You Can Do with VerdiWow it's been a while, but I'm back with a new series of YouTube videos. Hurray !!This time it's all about Verdi and all the cool things it can do for you.Since most of you guys already know it is the best debugger out there, my goal is to show you... » We Hear Ya! During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results: Verification Methodology - 41%SystemVerilog Tutorials - 31%e Tutorials - 13%Interviews - 12%... » Another Step Forward For VMMWhile the move from 1.0 to 1.1 and its later flavors did not involve a major paradigm shift, VMM1.2 (beta) introduces several fundamentally new concepts that you should be aware of. Some of the new concepts are the natural result of an evolving... » About UVM And YouThere’s been a lot of buzz about the lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers... » Method Manipulation In SV and eIf you're familiar with SystemVerilog and taking your first steps in e (or vice versa) you might find this useful. Here are some of the most common method manipulations that you''ll need to master and how you should go about implementing them in e... Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License. |
