More articles : » Ignorance Is A BlissThere is a rather confusing feature in Specman’s coverage engine that I would like to share with you today. I’ve met several people (including myself) who had been struggling to understand what was going on there and gave up Recently I was... » VMM Hackers Guide - Shutting Down Atomic GeneratorsEverybody likes atomic generators. If you have a vmm_data class, all you have to do is add a quick macro line and you get a free VMM-compliant generator that you only need to instantiate in your environment. An atomic generator is a simple yet... » To Randomize Or Not To RandomizeOne of my former colleagues once revealed the fact that she had no less than 70 pairs of shoes. That’s right, seventy! She had been very good at her job and by no means had any plans to start her own shoe business so I asked myself why on earth... » Educate Yourself - SystemVerilog 101SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get... » VMM Hackers Guide - Default Behavior For Your BFMHere's a short tutorial on how to implement a default behavior for your BFM using VMM. Some protocols require constant activity on their interface even when you don't have any data to transmit. This means you must have a mechanism that drives idle... Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
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