More articles : » Who Wants To Be A Verifier?Are you looking for a job in verification? Are you pursuing a career in verification? Congratulations! There a few things you might want to consider about your prospective employer before you sign the contract. In today's important article we'll try... » Get Organized Even On WindowsHere’s a cool (and free) application that can make your life a bit more organized if you tend to have many open windows. » Get HookedChanging an existing eVC for new project requirements is a grueling task. It’s really painful for any eVC developer to witness his creation being torn apart by an end user, but a little prudence from the developer can result into longevity of eVC.... » The Big PictureGreat verification engineers know the secret - if they want to be successful they must also understand the essence of the entire chip design flow, from concept to working samples. Here are some great videos that will help you see the big picture a... » Method Manipulation In SV and eIf you're familiar with SystemVerilog and taking your first steps in e (or vice versa) you might find this useful. Here are some of the most common method manipulations that you''ll need to master and how you should go about implementing them in e... Copyright © 2012 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License. |
|
