More articles : » Using Constrained-Random Verification with Legacy TestbenchesOne of SystemVerilog's noticeable features is that it is basically a "design language" that has been extended with verification capabilities. This might be an advantage or not, depending on who you're asking, but obviously, if you only want to use a... » Method Manipulation In SV and eIf you're familiar with SystemVerilog and taking your first steps in e (or vice versa) you might find this useful. Here are some of the most common method manipulations that you''ll need to master and how you should go about implementing them in e... » VMM Hackers Guide - Shutting Down Atomic GeneratorsEverybody likes atomic generators. If you have a vmm_data class, all you have to do is add a quick macro line and you get a free VMM-compliant generator that you only need to instantiate in your environment. An atomic generator is a simple yet... » VMM Hackers Guide - Creating Smart Scenarios With Atomic GeneratorsVMM ships with some pretty useful built-in components and applications. VMM''s Atomic Generator is probably one of the most powerful ones, yet it's pretty basic. It can definitely help you generate a flow of random items but it was not intended for... » Smart Constraints In SystemVerilogConstraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really... Copyright © 2012 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
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