More articles : » Top 10 Verification MythsLet’s unveil the truth behind some of the common myths out there! » Plug, Play and Reuse!Time to talk about module-to-system reuse, a very important topic. If you plan your verification environment properly (using one of the common methodologies in the market today or your own) you’ll be able to easily build a system level... » We Hear Ya! During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results: Verification Methodology - 41%SystemVerilog Tutorials - 31%e Tutorials - 13%Interviews - 12%... » Get HookedChanging an existing eVC for new project requirements is a grueling task. It’s really painful for any eVC developer to witness his creation being torn apart by an end user, but a little prudence from the developer can result into longevity of eVC.... » Educate Yourself - SystemVerilog 101SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get... Copyright © 2012 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
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