Home SystemVerilog EndMaker: Make Your SystemVerilog Code Look Professional (Free Utility)

Search

EndMaker: Make Your SystemVerilog Code Look Professional (Free Utility) PDF Print E-mail
User Rating: / 21
PoorBest 
Thursday, 15 April 2010 12:46

This is a cool little utility that will make your SystemVerilog look much more professional. It simply adds an end-of-method identifier (label) to every task or function so that every endfunction turns into endfunction : function_name (with the appropriate function_name of course.. Duh!) and endtask turns into endtask : task_name.  This really makes your code more readable and consistent.

How to use? very easy – download the file below and then simply run it on every file you wish to process, like this:

%./endmaker file.sv

 

Try it out now! Let us know what you think.

 

Note: when you save the file, sometimes an automatic file extension will be added, e.g. endmaker.txt. You can safely rename the file to get rid of it.


Attachments:
FileDescriptionFile size
Download this file (endmaker.txt)EndMakerAutomatic endfunction/entask label generator1 Kb
 
More articles :

» Top 10 Verification Myths

Let’s unveil the truth behind some of the common myths out there!

» Plug, Play and Reuse!

Time to talk about module-to-system reuse, a very important topic. If you plan your verification environment properly (using one of the common methodologies in the market today or your own) you’ll be able to easily build a system level...

» We Hear Ya!

 During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results: Verification Methodology - 41%SystemVerilog Tutorials - 31%e Tutorials - 13%Interviews - 12%...

» Get Hooked

Changing an existing eVC for new project requirements is a grueling task. It’s really painful for any eVC developer to witness his creation being torn apart by an end user, but a little prudence from the developer can result into longevity of eVC....

» Educate Yourself - SystemVerilog 101

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get...

Add comment


Security code
Refresh

Copyright © 2012 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.