More articles : » Smart Constraints In SystemVerilogConstraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really... » Don't Be SYSsyAnyone who’s ever worked with me knows that I have several weaknesses. One of them is extra sensitivity to things that reside under sys (global.sys) in Specman/e. If this is Chinese to you then you’re probably a SystemVerilog guy: "sys" is the... » Useful OVM-e SnippetsHow to activate Specman Profiler? How to get rid of automatic vr_ad coverage? Let's find out. » How To Validate Type-Casting In OVM-eBefore type-casting an e variable ("as_a"), we often want to check the validity of the operation (this is quite similar in concept to $cast in SystenVerilog). The reason is simple, in case the casting operation failed we would end up with a fatal... » VMM Hackers Guide - Shutting Down Atomic GeneratorsEverybody likes atomic generators. If you have a vmm_data class, all you have to do is add a quick macro line and you get a free VMM-compliant generator that you only need to instantiate in your environment. An atomic generator is a simple yet... Copyright © 2012 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
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