SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language seems to be ubiquitous and all 3 big EDA vendors keep pushing it forward.  Whether this is good or bad is an interesting question, but one thing is certain - if you consider yourself a modern verifier, you'd better get familiar with SystemVerilog unless you want to stay in the dark.

There’s been a lot of buzz about the UVM lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers questioned the need for adopting any verification methodology… Today, however, the question is entirely different – it is WHICH methodology to adopt. So as the UVM is gradually taking form and drawing the attention of verification stakeholders I think it’s a great time to stop and remind ourselves why we need a verification methodology in the first place, and more importantly - what makes a verification methodology so good that the only question about it would be “how quickly can I learn it”?  I have identified 3 elements of a good verification methodology that work together, each on a separate track, to make it do its magic. The first element is Guidance, the second is Efficiency, and the third one – perhaps the most exciting one – is what I call The Real Added Value.

Things are changing. The EDA industry is undergoing a paradigm shift. John Bruggerman’s visionary document talks about the application-driven market and how EDA should become its enabler and Janick Bergeron's inspiring talk at SNUG San Jose gives us a glimpse of the future of verification. One of the major challenges we’re already facing today is an increasing number of IP blocks in a single system. Designs are getting bigger and bigger, and the focus is shifting towards system level integration rather than “design creation”.