SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language seems to be ubiquitous and all 3 big EDA vendors keep pushing it forward. Whether this is good or bad is an interesting question, but one thing is certain - if you consider yourself a modern verifier, you'd better get familiar with SystemVerilog unless you want to stay in the dark.
Yes we've upgraded our website! We hope you like the new look and feel. A new decade has just begun and we feel that 2010 is going to be a great year. So what can we expect in 2010? Yet again, the EDA industry has termed a new acronym for us - UVM. VMM and OVM are so 2009... UVM (Unified Verification Methodology) is the new name of the game. Well, at least as far as SystemVerilog users are concerned. Take some OVM, add a bit of VMM, one month in the oven, put some sugar on top and you got yourself a "brand new" industry standard methodology for System Verilog. We talked about this last year - how convergence on methodology is inevitable - and we're glad to see it starting to happen more quickly than we had thought.
Got 2 minutes? Watch Yaron's cool presentation about the 7 secrets of practical verification where he''ll tell you how to make your verification project a big success. You can also download the slides here.
Your tool provider won’t tell you that, nor will those fancy methodology books, but verification is not all about mastering technical skills. True, those will help you very much in your daily work but verification is first and foremost TEAM WORK. But not only that, there are several key factors, or qualities if you will, that really distinguish the great verification teams from the good ones. Here there are:
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